Epson RX-8564LC Uživatelský manuál Strana 1

RM0403-3-E01 Application Manual Real Time Clock Mod

RX − 8564 LC Page − 7 ETM12E-01 9. Reference data (1) Example of frequency and temperature characteristics -150-100-500-50 0 50 100Temperature [°

RX − 8564 LC Page − 8 ETM12E-01 10. External connection example device SCLSDAGNDVDDMaster VDD SCLSDAtrR =CBUSPull up Registor8564 SCLSDAGNDVDDSLA

RX − 8564 LC Page − 9 ETM12E-01 11. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. Car

RX − 8564 LC Page − 10 ETM12E-01 12. Overview of Functions and Description of Registers 12.1. Overview of Functions 1) Clock functions This

RX − 8564 LC Page − 11 ETM12E-01 12.2. Register table Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 note 00 Control 1

RX − 8564 LC Page − 12 ETM12E-01 13. Description of Functions 13.1. Description of registers 13.1.1. Control register 1 ( Reg − 00 [h] )

RX − 8564 LC Page − 13 ETM12E-01 13.1.2. Control register 2 ( Reg − 01 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit

RX − 8564 LC Page − 14 ETM12E-01 13.1.3. Clock counter ( Reg − 02 [h] to 04 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2

RX − 8564 LC Page − 15 ETM12E-01 13.1.4. Calendar counter ( Reg − 05 [h] , 07 [h] , 08 [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit

RX − 8564 LC Page − 16 ETM12E-01 13.1.6. Alarm registers ( Reg − 09 [h] to 0C [h] ) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2

NOTICE • The material is subject to change w

RX − 8564 LC Page − 17 ETM12E-01 13.1.9. CLKOUT output register (Reg - 0D [h]) Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit

RX − 8564 LC Page − 18 ETM12E-01 13.2. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt function generates an interrupt event

RX − 8564 LC Page − 19 ETM12E-01 3) Overview of fixed-cycle timer interrupt function (1) Changing the TE (Timer Enable) bit value from "0&

RX − 8564 LC Page − 20 ETM12E-01 13.2.2. Related registers for function of timer interrupts. Address [h] Function bit 7 bit 6 bit 5 bit 4 bi

RX − 8564 LC Page − 21 ETM12E-01 3) Down counter for fixed-cycle timer ( Timer Register ) This register is used to set the default (preset) valu

RX − 8564 LC Page − 22 ETM12E-01 6) TIE bit ( Timer Interrupt Enable ) This bit is used to control output of interrupt signals from the /INT pin

RX − 8564 LC Page − 23 ETM12E-01 13.2.4. Diagram of fixed-cycle timer interrupt function 13.2.4.1. Operation example of level interrupt mode ( TI

RX − 8564 LC Page − 24 ETM12E-01 13.2.4.2. Operation example of repeated interrupt mode ( TI / TP = " 1 " ) • After an interrupt event

RX − 8564 LC Page − 25 ETM12E-01 13.3. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm setti

RX − 8564 LC Page − 26 ETM12E-01 13.3.2. Alarm interrupt function registers Address [h] Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1

RX − 8564 LC CONTENTS 1. Overview...

RX − 8564 LC Page − 27 ETM12E-01 3) AIE bit ( Alarm Interrupt Enable ) This bit is used to control interrupt signal output from the /INT pin when

RX − 8564 LC Page − 28 ETM12E-01 13.4. /INT "L" Interrupt Output When Interrupt Function Operates 1) Setting interrupt events to occur i

RX − 8564 LC Page − 29 ETM12E-01 13.5. Flow Charts • The flow charts shown below are intended as examples only. ∗ These examples are written t

RX − 8564 LC Page − 30 ETM12E-01 3) Example of processing to recover from backup mode ∗1) Check the VL bit (Voltage Low Flag). ∗2) When

RX − 8564 LC Page − 31 ETM12E-01 6) Example of timer interrupt function setting To next process Set timer interrupt function TE ← " 0

RX − 8564 LC Page − 32 ETM12E-01 13.6. Reading/Writing Data via the I2C Bus Interface 13.6.1. Overview of I2C-BUS The I2C bus supports bi-direct

RX − 8564 LC Page − 33 ETM12E-01 13.6.3. Starting and stopping I2C bus communications SCL START condition SDA 1 s ( Max. ) Repeated START(RESTART

RX − 8564 LC Page − 34 ETM12E-01 13.6.4. Data transfers and acknowledge responses during I2C-BUS communications 1) Data transfers Data transf

RX − 8564 LC Page − 35 ETM12E-01 13.6.6. I2C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the

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RX − 8564 LC Page − 1 ETM12E-01 Low power consumption / Small size thin model package I2C-Bus Interface Real Time Clock Module RX −−−− 8

RX − 8564 LC Page − 2 ETM12E-01 3. Terminal description 3.1. Terminal connections RX − 8564 LC 1.N.C. 12.N.C. 2.N.C. 11. CLKOE3.N.C. 10. VDD 4.

RX − 8564 LC Page − 3 ETM12E-01 4. External Dimensions / Marking Layout 4.1. External Dimensions RX − 8564 LC ( VSOJ − 12pin ) • External di

RX − 8564 LC Page − 4 ETM12E-01 5. Absolute Maximum Ratings GND = 0 V Parameter Symbol Condition Rating Unit Supply Voltage VDD Between VDD a

RX − 8564 LC Page − 5 ETM12E-01 8. Electrical Characteristics 8.1. DC characteristics * Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5

RX − 8564 LC Page − 6 ETM12E-01 8.2. AC electrical characteristics * Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to