Epson S1C33210 Uživatelský manuál stáhnout pdf (Strana 202)

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101

II CORE BLOCK: ITC (Interrupt Controller)

B-II-5-4 EPSON S1C33210 FUNCTION PART

Trap Table

The C33 Core Block allows the base (starting) address of the trap table to be set by the TTBR register.

TTBR0 (D[9:0]) / TTBR low-order register (0x48134): Trap table base address [9:0] (fixed at "0")

TTBR1 (D[F:A]) / TTBR low-order register (0x48134): Trap table base address [15:10]

TTBR2 (D[B:0]) / TTBR high-order register (0x48136):Trap table base address [27:16]

TTBR3 (D[F:C]) / TTBR high-order register (0x48136):Trap table base address [31:28] (fixed at "0")

After an initial reset, the TTBR register is set to 0x0C00000.

Therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the

above address.

TTBR0 and TTBR3 are read-only bits which are fixed at "0". Therefore, the trap table starting address always begins

with a 1KB boundary address.

The TTBR register is normally write-protected to prevent them from being inadvertently rewritten. To remove this

write protection function, another register, TBRP (D[7:0]) / TTBR write-protect register (0x4812D [byte]), is

provided. A write to the TTBR register is enabled by writing "0x59" to TBRP and is disabled back again by a write

to the most significant byte of the TTBR register (0x48137). Consequently, a write to the TTBR register needs to

begin with the low-order half-word first. However, since an occurrence of NMI or the like between writes of the

low-order and high-order half-words would cause a malfunction, it is recommended that the register be written in

words.

1 2 ... 197 198 199 200 201 202 203 204 205 206 207 ... 558 559

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