Epson ARM.POWERED ARM720T manuály

Epson ARM.POWERED ARM720T Uživatelský manuál (224 strany)

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ARM720T Revision 4

1

Contents

5

7 Memory Management Unit

6

List of Figures

8

List of Tables

10

CONTENTS

11

About this document

15

Typographical conventions

16

Product revision status

16

AMBA Specification (Rev 2.0)

17

Introduction

19

1 Introduction

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1: Introduction

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1.1.1 EmbeddedICE-RT logic

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1.2 Coprocessors

25

1.3 About the instruction set

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1.3.1 Format summary

26

1.3.2 ARM instruction set

27

Table 1-3 Addressing mode 2

30

Table 1-11 Condition fields

33

1.3.3 Thumb instruction set

34

1.4 Silicon revisions

38

Programmer’s Model

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2 Programmer’s Model

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2.2 Memory formats

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2.3 Instruction length

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2.4 Data types

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2.5 Operating modes

44

2.6 Registers

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2: Programmer’s Model

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Stack Pointer

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Link Register

46

2.7 Program status registers

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2.7.3 Reserved bits

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2.8 Exceptions

50

2.8.4 Fast interrupt request

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2.8.5 Interrupt request

52

2.8.6 Abort

52

2.8.7 Software interrupt

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2.8.8 Undefined instruction

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2.8.9 Exception vectors

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2.8.10 Exception priorities

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2.8.11 Exception restrictions

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Fast Context Switch Extension

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Process IDentifier

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2.10 Reset

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2.11.2 Early termination

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Configuration

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3 Configuration

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3: Configuration

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3.3 Registers

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3.3.2 Control Register

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3.3.5 Fault Status Register

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3.3.6 Fault Address Register

67

3.3.8 TLB Operations Register

67

3.3.10 Register 14, reserved

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3.3.11 Test Register

69

Instruction and

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Data Cache

71

4 Instruction and Data Cache

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4.2 IDC validity

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Write Buffer

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5 Write Buffer

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5.2 Write buffer operation

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The Bus Interface

79

6 The Bus Interface

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Address and control signals

82

AMBA Specification (Rev

82

6.2 Bus interface signals

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6: The Bus Interface

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6.3 Transfer types

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6.4.1 HADDR[31:0]

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6.4.2 HWRITE

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6.4.3 HSIZE[2:0]

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6.4.4 HBURST[2:0]

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6.4.5 HPROT[3:0]

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6.5.1 HREADY

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6.6 Data buses

90

6.6.2 HRDATA[31:0]

91

6.6.3 Endianness

91

6.7 Arbitration

92

6.8 Bus clocking

93

6.9 Reset

93

Memory Management

95

7.1.2 Translated entries

98

7.3 Address translation

100

Level one fetch

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Level two fetch

101

7.3.2 Level one fetch

102

7.3.3 Level one descriptor

102

7: Memory Management Unit

103

7.3.4 Section descriptor

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7.3.8 Level two descriptor

106

Table indexTranslation base

108

7.3.12 Subpages

110

7.4 MMU faults and CPU aborts

111

7.5.1 Fault Status

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7.6 Domain access control

113

Access Permission

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7.7 Fault checking sequence

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7.7.2 Translation fault

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7.7.3 Domain fault

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7.7.4 Permission fault

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7.8 External aborts

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THIS PAGE IS BLANK

118

Coprocessor Interface

119

8 Coprocessor Interface

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8: Coprocessor Interface

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8.4.1 The coprocessor

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8.4.2 The ARM720T core

125

8.4.3 Coprocessor signaling

126

8.5 Connecting coprocessors

129

8.7 STC operations

130

8.8 Undefined instructions

130

8.9 Privileged instructions

130

Debugging Your System

131

9 Debugging Your System

133

9.1.1 A typical debug system

134

9.2 Controlling debugging

135

9.2.1 Debug modes

136

9.3 Entry into debug state

137

9: Debugging Your System

138

Programming breakpoints

139

Programming watchpoints

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9.3.5 Clocks

140

9.4 Debug interface

141

Watchpoint unit registers

142

9.7 Disabling EmbeddedICE-RT

143

9.9 Monitor mode debugging

144

Abort status register

145

Debug control register

145

Debug Communication Channel

146

Communications through the

146

Test Access Port

149

Boundary-Scan Architecture

149

Test data registers

149

Instruction register

150

The TAP controller

150

9.12 The TAP controller

151

9.13 Public JTAG instructions

152

9.13.3 IDCODE (b1110)

153

9.13.4 BYPASS (b1111)

153

9.13.5 RESTART (b0100)

153

9.14 Test data registers

154

9.14.3 Instruction register

155

9.14.5 Scan chains 1 and 2

156

9.15 Scan timing

157

Debug status register

160

Exit from debug state

160

9.17 Exit from debug state

161

9.18.1 Breakpoints

162

9.18.2 Watchpoints

162

9.18.4 Debug request

163

9.18.5 System speed access

163

Interrupts

164

Data Aborts

164

9.19.2 Interrupts

165

9.19.3 Data Aborts

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8 67 5 34 2 01

167

9.21 Programming breakpoints

168

9.21.2 Software breakpoints

169

9.22 Programming watchpoints

170

9.23 Abort status register

170

9.24 Debug control register

171

9.24.1 Disabling interrupts

172

9.24.2 Forcing DBGRQ

172

9.24.3 Forcing DBGACK

172

9.25 Debug status register

173

9.27 EmbeddedICE-RT timing

176

ETM Interface

177

10 ETM Interface

179

ARM720T processor

180

10.4 Clocks and resets

181

10.5 Debug request wiring

181

10.6 TAP interface wiring

181

Test Support

183

11 Test Support

185

11: Test Support

186

11.3 Test State Register

187

Translation Table Base

192

Domain Access Control

192

Fault Status Register

192

Fault Address Register

192

31 654 0

194

MVA TAG V P

194

SBZSIZE_C

194

Base SBZ

196

2526 20 19 1

196

Appendix A

199

Signal Descriptions

199

A Signal Descriptions

201

A: Signal Descriptions

202

A.3 JTAG and test signals

203

A.4 Debugger signals

204

A.6 ATPG test signals

207

A.7 Miscellaneous signals

207

Glossary

209

See also

216

ARM DDI 0229B EPSON Index-1

219

Index-2 EPSON ARM DDI 0229B

220

ARM DDI 0229B EPSON Index-3

221

Index-4 EPSON ARM DDI 0229B

222

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