Epson S1C63558 Specifikace Strana 65
- Strana / 144
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
S1C63466 TECHNICAL MANUAL EPSON 55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LPAGE: LCD display memory selection register (FF61H•D0)
Selects the display memory area at 1/8 duty drive.
When "1" is written: F100H–F177H
When "0" is written: F000H–F077H
Reading: Valid
By writing "1" to the LPAGE register, the data set in F100H–F177H (the second half of the display
memory) is displayed, and when "0" is written, the data set in F000H–F077H (the first half of the display
memory) is displayed.
This function is valid only when 1/8 duty is selected, and when 1/16 or 1/17 duty is selected, this
register can be used as a general purpose register.
At initial reset, this register is set to "0".
LC3–LC0: LCD contrast adjustment register (FF62H)
Adjusts the LCD contrast.
LC3–LC0 = 0000B light
::
LC3–LC0 = 1111B dark
At room temperature, use setting number 7 or 8 as standard.
When the LCD drive voltage is supplied from outside by the mask option selection, this adjustment
becomes invalid.
At initial reset, LC0–LC3 are undefined.
4.7.8 Programming notes
(1) When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H, F203H,
· · ·, F277H) is made, the operation is not guaranteed.
(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,
there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF
because these are set so that the display goes OFF.
- S1C63466 1
- CONTENTS 7
- EPSON iii 9
- 1OUTLINE 11
- 1.2 Block Diagram 12
- 1.3 Pin Layout Diagram 13
- 1.4 Pin Description 15
- 1.5 Mask Option 16
- CHAPTER 1: OUTLINE 17
- 2.1 Power Supply 19
- 2.2 Initial Reset 21
- 2.3 Test Terminal (TEST) 23
- 3 CPU, ROM, RAM 24
- 3.4 Data ROM 25
- CHAPTER 4 26
- ERIPHERAL 26
- PERATION 26
- ∗2 Not set in the circuit 27
- EPSON 19 29
- EPSON 21 31
- 4.2 Watchdog Timer 32
- 4.2.4 Programming notes 33
- 4.3 Oscillation Circuit 34
- (sound quality) 35
- EPSON 27 37
- 4.3.7 Programming notes 38
- 4.4.2 Interrupt function 39
- 4.4.3 Mask option 40
- EPSON 31 41
- 4.4.5 Programming notes 43
- 4.5.2 Mask option 44
- 4.5.3 High impedance control 45
- 4.5.4 Special output 45
- •TOUT (R02) 46
- • FOUT (R03) 46
- EPSON 37 47
- 4.5.6 Programming notes 49
- 4.6.2 Mask option 51
- 4.6.6 I/O memory of I/O ports 53
- (2) I/O port control 55
- 4.6.7 Programming notes 56
- EPSON 47 57
- 4.7.3 Mask option 58
- EPSON 49 59
- 4.7.5 Display memory 61
- 4.7.6 LCD contrast adjustment 62
- EPSON 53 63
- 4.7.8 Programming notes 65
- 4.8 Clock Timer 66
- 4.8.3 Interrupt function 67
- EPSON 59 69
- 4.8.5 Programming notes 70
- 4.9 Stopwatch Timer 71
- 4.9.3 Interrupt function 72
- EPSON 63 73
- 4.9.5 Programming notes 74
- 4.10 Programmable Timer 75
- 4.10.3 Counter mode 77
- (1) Selection of source clock 78
- Timer 1 underflow 80
- Source clock for serial I/F 80
- EPSON 71 81
- EPSON 73 83
- EPSON 75 85
- 4.10.9 Programming notes 86
- EPSON 77 87
- 4.11.2 Mask option 88
- EPSON 79 89
- SD3 SD2 SD1 SD0 90
- SD4 SD5 SD6 SD7 90
- SD7 SD6 SD5 SD4 90
- SD0 SD1 SD2 SD3 90
- (5) Timing chart 91
- EPSON 83 93
- SS) level 94
- DD) level bit 94
- 4.11.6 Programming notes 95
- 4.12 Sound Generator 96
- 4.12.6 One-shot output 99
- *2 Not set in the circuit 100
- EPSON 91 101
- 4.12.8 Programming notes 102
- Data bus 103
- 4.13.5 Programming notes 105
- 4.14 Interrupt and HALT 106
- EPSON 97 107
- 4.14.1 Interrupt factor 108
- EPSON 99 109
- EPSON 101 111
- 4.14.5 Programming notes 112
- 5SUMMARY OF NOTES 113
- Memory and stack 114
- Watchdog timer 114
- Oscillation circuit 114
- Input port 115
- Output port 115
- I/O port 115
- LCD driver 115
- Clock timer 115
- Stopwatch timer 116
- Programmable timer 116
- Serial interface 116
- Sound generator 117
- SVD circuit 117
- Interrupt 117
- 7ELECTRICAL CHARACTERISTICS 119
- 7.3 DC Characteristics 120
- CR oscillation frequency f 124
- <Master mode> 125
- <Slave mode> 125
- 2.5 msec min 126
- 5 msec min 126
- CHAPTER 8PACKAGE 127
- QFP17-144pin 128
- QFP5-128pin 129
- QFP8-144pin 130
- CHAPTER 9PAD LAYOUT 133
- CHAPTER 9: PAD LAYOUT 134
- APPENDIX S5U1C63000P MANUAL 135
- OSC1 rough adjustment 136
- OSC1 fine adjustment 136
- OSC3 rough adjustment 136
- OSC3 fine adjustment 136
- (7) RESET switch 137
- (9) IOSEL2 137
- (10) CLK and PRG switch 137
- (11) VC5 137
- I/O connection cable 138
- To target board 138
- A.3 Usage Precautions 140
- (3) Functional precautions 141
- First issue July, 1998 144
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