Epson SED 1520 Series Uživatelský manuál

SED1520 SeriesLCD driver with RAMTechnical Manual

SED1520 SeriesEPSON 2–7SED1520Series(3) LCD Drive Circuit SignalsName DescriptionCL Input. Effective for an external clock operation model only.This

SED1520 Series2–8 EPSONlevel after reset (see Table 1).When the CS signal is high, the SED1520 series isdisconnected from the MPU bus and set to stand

SED1520 SeriesEPSON 2–9SED1520SeriesFigure 1 Bus Buffer DelayBusy flagWhen the Busy flag is logical 1, the SED1520 series isexecuting its internal o

SED1520 Series2–10 EPSONCommon Timing Generator CircuitGenerates common timing signals and FR frame signalsfrom the CL basic clock. The 1/16 or 1/32

SED1520 SeriesEPSON 2–11SED1520Series*1 If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lowerfreque

SED1520 Series2–12 EPSONCOM 0COM 1COM 2COM 3COM 4COM 5COM 6COM 7COM 8COM 9COM 10COM 11COM 12COM 13COM 14COM 15COM 16COM 17COM 18CO

SED1520 SeriesEPSON 2–13SED1520SeriesCOM0COM1COM2COM3COM4COM5COM6COM7COM8COM9COM10COM11COM12COM13COM14COM15SEG0SEG1SEG2SEG3SEG40123 150001231122333115

SED1520 Series2–14 EPSONCodeCommandA0RD WRD7 D6 D5 D4 D3 D2 D1 D0Display On/OFF 0 1 0 1 0 1 0 1 1 1 0/1Display start line 0 1 0 1 1 0 Display start ad

SED1520 SeriesEPSON 2–15SED1520SeriesCommand DescriptionTable 3 is the command table. The SED1520 series identifies a data bus using a combination of

SED1520 Series2–16 EPSONSet Column AddressThis command specifies a column address of the display data RAM. When the display data RAM is accessed by t

NOTICENo parts of this material may be reproduced or duplicated in any form or by any means without the writtenpermission of Seiko Epson. Seiko Epson

SED1520 SeriesEPSON 2–17SED1520SeriesRead Display DataReads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display

SED1520 Series2–18 EPSONRead-Modify-WriteThis command defeats column address register auto-increment after data reads. The current conetents of the c

SED1520 SeriesEPSON 2–19SED1520SeriesResetThis command clears• the display start line register.• and set page address register to 3 page.It does not a

SED1520 Series2–20 EPSONSPECIFICATIONSAbsolute Maximum RatingsParameter Symbol Rating UnitSupply voltage (1) VSS –8.0 to +0.3 VSupply voltage (2) V5 –

SED1520 SeriesEPSON 2–21SED1520SeriesDC Characteristics (Cont’d)Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwiseRatingParameter Symbol Conditi

SED1520 Series2–22 EPSONRelationship between fOSC, fFR and Rf, and operating bounds on VSS and V5*9 • Relationship between oscillation frequency, fram

SED1520 SeriesEPSON 2–23SED1520SeriesAC Characteristics• MPU Bus Read/Write I (80-family MPU)Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated ot

SED1520 Series2–24 EPSON• MPU Bus Read/Write II (68-family MPU)Ta = –20 to 75 deg. C, VSS = –5 V ±10 unless stated otherwiseRatingParameter Symbol Con

SED1520 SeriesEPSON 2–25SED1520Series• Display Control Signal TimingInputTa = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwiseRatingParamet

SED1520 Series2–26 EPSONAPPLICATION NOTESMPU Interface Configuration80 Family MPURESETVDDVCCV5VSSSED1520FAAGNDMPUDecoderRESWRRDD0 to D7CSA0RESWRRDD0 t

– i –SED1520 SeriesSED1520SeriesContentsOVERVIEW ...

SED1520 SeriesEPSON 2–27SED1520SeriesLCD Drive Interface ConfigurationSED1520F0A–SED1520F0ASED1522F0A–SED1522F0ASED1520FAA–SED1520FAASED1522FAA–SED152

SED1520 Series2–28 EPSONSED1520FAA–SED1521FAANotes: 1. The duty cycle of the slave must be the same as that for the master.2. If a system has two or m

SED1520 SeriesEPSON 2–29SED1520SeriesLCD Panel Wiring Example (The full-dot LCD panel displays a character in 6×××××8 dots.)1/16 duty:• 10 characters

SED1520 Series2–30 EPSONPackage Dimensions• Plastic QFP5–100 pinDimensions: inches (mm)• Plastic QFP15–100 pin80 510.110(2.8)0~12°18150100 31300.026

SED1520 SeriesEPSON 2–31SED1520SeriesSpecifications • Base: U-rexS, 75µm • Copper foil: Electrolytic copper foil, 35µm • Sn plating • Product pitc

SED1520 SeriesEPSON 2–1SED1520SeriesOVERVIEWThe SED1520 family of dot matrix LCD drivers aredesigned for the display of characters and graphics. Thed

SED1520 Series2–2 EPSONA0,CSDisplay data latch circuitLCD drive circuitCommon counterDisplay start line registerLine counterLine address decoderColumn

SED1520 SeriesEPSON 2–3SED1520SeriesPACKAGE OUTLINEQFP5QFP15Note: This is an example of SED1520F pin assignment. The modified pin names are given bel

SED1520 Series2–4 EPSONPADPad ArrangementChip specifications of AL pad packageChip size: 4.80×7.04×0.400 mmPad pitch: 100×100 µmChip specifications of

SED1520 SeriesEPSON 2–5SED1520Series1 COM5 159 65072 COM6 159 63083 COM7 159 61084 COM8 159 59095 COM9 159 57096 COM10 159 55107 COM11 159 53108 COM12

SED1520 Series2–6 EPSONPIN DESCRIPTION(1) Power PinsName DescriptionVDD Connected to the +5Vdc power. Common to the VCC MPU power pin.VSS 0 Vdc pin