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Strany 1 - S1C6S2N7

MF881-02Technical ManualCMOS 4-BIT SINGLE CHIP MICROCOMPUTERS1C6S2N7 Technical Hardware/S1C6S2N7 Technical SoftwareS1C6S2N7

Strany 2

I-ii EPSON S1C6S2N7 TECHNICAL HARDWARECONTENTSCHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ... I-134.1 Memory Map ...

Strany 3

I-88 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 7: PACKAGECHAPTER 7 PACKAGE7.1 Plastic PackageQFP6-60pinIndex466011545 31301614.017.6±0.2±0.414.017.6±0.

Strany 4

S1C6S2N7 TECHNICAL HARDWARE EPSON I-89CHAPTER 7: PACKAGE7.2 Ceramic Package for Test SamplesQFP6-60pinIndex466011545 31301613.9717.00±0.15±0.313.9717.

Strany 5

I-90 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 8: PAD LAYOUTCHAPTER 8 PAD LAYOUT8.1 Diagram of Pad LayoutYX(0, 0)3520151015253040455055Die No.Chip size

Strany 6

S1C6S2N7 TECHNICAL HARDWARE EPSON I-91CHAPTER 8: PAD LAYOUT8.2 Pad Coordinates(Unit: µm)Pad No.1234567891011121314151617181920212223242526272829Pad No

Strany 8

SoftwareS1C6S2N7II. Technical Software

Strany 10 - CONTENTS

SoftwareS1C6S2N7 TECHNICAL SOFTWARE EPSON II-iCONTENTSCONTENTSCHAPTER 1 CONFIGURATION ... II-1

Strany 11 - Hardware

II-ii EPSON S1C6S2N7 TECHNICAL SOFTWARECONTENTS3.4 I/O Ports ... II-24I/O port m

Strany 12

SoftwareS1C6S2N7 TECHNICAL SOFTWARE EPSON II-iiiCONTENTSCHAPTER 4 SUMMARY OF PROGRAMMING POINTS... II-66APPENDIX A Table of Instru

Strany 13 - CHAPTER 1

HardwareS1C6S2N7 TECHNICAL HARDWARE EPSON I-iiiCONTENTS4.8 Stopwatch Timer ... I-49Configura

Strany 15 - Core CPU S1C6200A

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-1CHAPTER 1: CONFIGURATIONCHAPTER 11.1CONFIGURATIONS1C6S2N7 Block DiagramSVDPowerController LCDDriverRAM80 × 4 Int

Strany 16 - Pin Layout Diagram

II-2 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 1: CONFIGURATIONROM MapThe S1C6S2N7 has a built-in mask ROM with a capacity of1,536 steps × 12 bits for

Strany 17 - Pin Description

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-3CHAPTER 1: CONFIGURATIONInterrupt VectorsWhen an interrupt request is received by the CPU, the CPUinitiates the

Strany 18 - Power Supply

II-4 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 1: CONFIGURATIONData Memory MapThe S1C6S2N7 built-in RAM has 80 words of data memory,32 words of display

Strany 19 - LCD system regulated

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-5CHAPTER 1: CONFIGURATIONTable 1.4.1(a) I/O memory map 1*1 Initial value following initial reset*2 Not set in th

Strany 20 - Initial Reset

II-6 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 1: CONFIGURATIONTable 1.4.1(b) I/O memory map 2Address CommentRegisterD3 D2 D1 D0 Name SR*1100E8H0EAH0E

Strany 21 - Simultaneous high input

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-7CHAPTER 1: CONFIGURATIONTable 1.4.1(c) I/O memory map 3Address CommentRegisterD3 D2 D1 D0 Name SR*1100EEH0EFH0

Strany 22 - Test Pin (TEST)

II-8 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 1: CONFIGURATIONTable 1.4.1(d) I/O memory map 4*1 Initial value following initial reset*2 Not set in th

Strany 23 - CHAPTER 3

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-9CHAPTER 1: CONFIGURATIONTable 1.4.1(e) I/O memory map 5*1 Initial value following initial reset*2 Not set in th

Strany 24 - ROM configuration

I-iv EPSON S1C6S2N7 TECHNICAL HARDWARECONTENTS6.3 DC Characteristics ... I-776.4 Analog Circuit

Strany 25 - AND OPERATION

II-10 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 2: INITIAL RESETINITIAL RESETInternal Register Status on Initial ResetFollowing an initial reset, the i

Strany 26 - Table 4.1.1(a) I/O memory map

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-11CHAPTER 2: INITIAL RESETAfter an initial reset, the program counter page (PCP) isinitialized to 1H, and the pro

Strany 27 - Table 4.1.1(b) I/O memory map

II-12 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 2: INITIAL RESETInitialize Program ExampleThe following is a program that clears the RAM and LCD,resets

Strany 28 - Table 4.1.1(c) I/O memory map

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-13CHAPTER 2: INITIAL RESET;LD X,0 ;LD Y,0 ;LD A,0 ;LD B,0 ;RST F,0 ;EI ;Enable interruptThe above program is a ba

Strany 29 - Table 4.1.1(d) I/O memory map

II-14 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)PERIPHERAL CIRCUITSDetails on how to control the S1C6S2N7 periphera

Strany 30 - Table 4.1.1(e) I/O memory map

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-15CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)The S1C6S2N7 has one 4-bit input port (K00–K03). Inputport data can

Strany 31 - Oscillation Circuit

II-16 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)• Bit-unit checking of input portsLabel Mnemonic/operand CommentDI

Strany 32 - Input Ports (K00–K03)

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-17CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)Output Ports3.2Output portmemory mapTable 3.2.1 I/O memory map*1 I

Strany 33 - Data bus

II-18 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)• Loading B register data into R00–R03Label Mnemonic/operand Comme

Strany 34 - Mask option

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-19CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)• Bit-unit operation of output portsLabel Mnemonic/operand Comment

Strany 35 - Control of input port

S1C6S2N7 TECHNICAL HARDWARE EPSON I-1CHAPTER 1: INTRODUCTIONINTRODUCTIONEach member of the S1C6S2N7 Series of single chip micro-computers features a 4

Strany 36

II-20 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)Special Use Output Ports3.3Special use outputport memo

Strany 37 - Output Ports (R00–R03)

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-21CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)In addition to the regular DC, special output can be s

Strany 38

II-22 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)• Buzzer driver output (BUZZER)When output port R01 is

Strany 39 - EPSON I-27

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-23CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)Table 3.3.3Mask option and registerselection• Internal

Strany 40 - Control of output

II-24 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)3.4 I/O PortsI/O port memorymapTable 3.4.1 I/O memory map*1 Initial v

Strany 41 - FOUT output

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-25CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)The S1C6S2N7 contains a 4-bit general I/O port (4 bits × 1).This port

Strany 42 - BUZZER output

II-26 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)• Loading P00–P03 input data into A registerLabel Mnemonic/operand Co

Strany 43 - I/O Ports (P00–P03)

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-27CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)• Loading P00–P03 output data into A registerLabel Mnemonic/operand C

Strany 44 - Control of I/O port

II-28 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)• Loading contents of B register into P00–P03Label Mnemonic/operand C

Strany 45

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-29CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)LCD Driver3.5LCD driver memorymapFig. 3.5.1Display memory mapAddress

Strany 46

I-2 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 1: INTRODUCTIONFeaturesCrystal or CR oscillation circuit, 32.768 kHz (typ.)100 instructions1,536 words ×1

Strany 47 - Configuration of LCD

II-30 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)The S1C6S2N7 contains 128 bits of display memory inaddresses 090H to

Strany 48 - Frame frequency

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-31CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)Fig. 3.5.37-segment LCD assignmentIn the assignment shown in Figure

Strany 49 - 1/3 duty (1/3 bias)

II-32 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)• Displaying 7-segmentThe LCD display routine using the assignment o

Strany 50 - 1/2 duty (1/3 bias)

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-33CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)• Bit-unit operation of the display memoryLabel Mnemonic/operand Com

Strany 51 - LCD lighting status

II-34 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Timer)3.6 TimerTimer memory mapTable 3.6.1 I/O memory mapAddress CommentRegiste

Strany 52

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-35CHAPTER 3: PERIPHERAL CIRCUITS (Timer)The S1C6S2N7 contains a timer with a basic oscillation of32.768 kHz (typi

Strany 53 - LCD static drive waveform

II-36 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Timer)• Initializing the timerLabel Mnemonic/operand CommentLD Y,0F9H ;Set addr

Strany 54 - Segment allocation

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-37CHAPTER 3: PERIPHERAL CIRCUITS (Timer)• Checking timer edgeLabel Mnemonic/operand CommentLD X,TMSTAT ;Set addre

Strany 55 - EPSON I-43

II-38 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)3.7 Stopwatch TimerStopwatch timermemory mapTable 3.7.1 I/O mem

Strany 56 - Fig. 4.6.9

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-39CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)The S1C6S2N7 contains 1/100 sec and 1/10 sec stopwatchtimers.Th

Strany 57 - Clock Timer

S1C6S2N7 TECHNICAL HARDWARE EPSON I-3CHAPTER 1: INTRODUCTION1.3 Block DiagramSVDPowerController LCDDriverRAM80 × 4 InterruptGeneratorInput PortTest Po

Strany 58 - Register

II-40 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)Examples of stop-watch timer controlprogramNote• Initializing t

Strany 59 - Control of clock

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-41CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)• Loading the stopwatch timerLabel Mnemonic/operand CommentLD Y

Strany 60

II-42 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)Supply Voltage Detection (SVD) C

Strany 61 - Stopwatch Timer

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-43CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)Control of the SVDcircuitThe SVD

Strany 62 - Count-up pattern

II-44 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)Heavy load protec-tion functionN

Strany 63 - Interrupt function

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-45CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)The normal mode changes to the h

Strany 64 - Control of stopwatch

II-46 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)Examples of heavyload protection

Strany 65 - EPSON I-53

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-47CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)• Operation through the SVDON re

Strany 66

II-48 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)StartRETFLAG←0HLMOD?SVDDT?SVDDT?

Strany 67 - Configuration of SVD

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-49CHAPTER 3: PERIPHERAL CIRCUITS (Motor Driver)3.9 Motor DriverMotor drivermemory mapTable 3.9.1 I/O memory map0F

Strany 68

I-4 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 1: INTRODUCTION1.4Fig. 1.4.1Pin assignmentQFP6-60pinIndex466011545 313016Pin Layout Diagram12345678910111

Strany 69 - Operation of SVD

II-50 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Motor Driver)By writing 1 to the FTRG register (address 0FEH D1), themotor driv

Strany 70 - Operation of heavy

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-51CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)3.10 Interrupt and HaltTable 3.10.1(a) I/O memory mapInterru

Strany 71 - Control of SVD cir

II-52 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)Table 3.10.1(b) I/O memory mapAddress CommentRegisterD3 D2 D

Strany 72

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-53CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)The S1C6S2N7 supports four types of a total of 10interrupts.

Strany 73 - Stepping Motor Driver

II-54 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)• Interrupt factor flagsThis flag is set when any of the K00

Strany 74 - Drive pulse

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-55CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)This flag is set to "1" when a falling edge is det

Strany 75 - Control of motor

II-56 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)This flag is set to "1" when a falling edge is det

Strany 76

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-57CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)This flag is set to "1" after a motor drive sequen

Strany 77 - Interrupt and HALT

II-58 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)• Interrupt mask registersThe interrupt mask registers are r

Strany 78 - Interrupt flag

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-59CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)Consequently, when the input terminal is in the activestatus

Strany 79 - Interrupt factors

S1C6S2N7 TECHNICAL HARDWARE EPSON I-5CHAPTER 1: INTRODUCTION1.5Pin DescriptionPin NameVDDVSSVS1VL1VL2VL3CA–CBOSC1OSC2K00–K03P00–P03R00–R03SEG0–25COM0–

Strany 80 - Specific masks and

II-60 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)• Interrupt vector addressThe S1C6S2N7 interrupt vector addr

Strany 81 - CPU system clock

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-61CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)If the EI state is set without resetting the interrupt facto

Strany 82 - Control of interrupt

II-62 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)K00EIK00K01EIK01K02EIK02K03EIK03ISW0EISW0ISMDEISMDISW1EISW1I

Strany 83 - EPSON I-71

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-63CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)Examples of interruptand halt controlprogram• Restart from h

Strany 84 - CHAPTER 5

II-64 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)Interruption vector routineLabel Mnemonic/operand CommentORG

Strany 85 - 6S2B7/6S2L7

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-65CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)SW10RQ:LD Y,SWFSK ;Address of stopwatch interrupt;factor fla

Strany 86 - 6.1 Absolute Maximum Rating

II-66 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 4: SUMMARY OF PROGRAMMING POINTSCHAPTER 4• Core CPU• Power SupplySUMMARY OF PROGRAMMINGPOINTSAfter the

Strany 87 - S1C6S2A7

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-67CHAPTER 4: SUMMARY OF PROGRAMMING POINTS• Input Port – When modifying the input port from high level to lowleve

Strany 88 - S1C6S2B7

II-68 EPSON S1C6S2N7 TECHNICAL SOFTWARECHAPTER 4: SUMMARY OF PROGRAMMING POINTS• I/O Port – When the I/O port is set to the output mode and a low-impe

Strany 89 - 6.3 DC Characteristics

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-69CHAPTER 4: SUMMARY OF PROGRAMMING POINTS• Interrupt – Re-start from the HALT state is performed by the inter-ru

Strany 90

I-6 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 2: POWER SUPPLY AND INITIAL RESETPOWER SUPPLY AND INITIAL RESETCHAPTER 22.1Power SupplyWith a single exte

Strany 91 - EPSON I-79

II-70 EPSON S1C6S2N7 TECHNICAL SOFTWAREAPPENDIX A TABLE OF INSTRUCTIONSAPPENDIX A Table of InstructionsB1000001001101111111111111111111A1000111111101

Strany 92

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-71APPENDIX A TABLE OF INSTRUCTIONSB111111111111111111111111111111111111A0000111111111101111111111111111111119111

Strany 93 - EPSON I-81

II-72 EPSON S1C6S2N7 TECHNICAL SOFTWAREAPPENDIX A TABLE OF INSTRUCTIONSd3 d2, d2 d1, d1 d0, d0 C, C d3d3 C, d2 d3, d1

Strany 94

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-73APPENDIX A TABLE OF INSTRUCTIONSAbbreviations used in the explanations have the followingmeanings.A ...

Strany 95 - EPSON I-83

II-74 EPSON S1C6S2N7 TECHNICAL SOFTWAREAPPENDIX A TABLE OF INSTRUCTIONSNBP... New bank pointerNPP ... New page pointerPCB... Program counter ba

Strany 96

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-75APPENDIX B THE S1C6S2N7 I/O MEMORY MAPAPPENDIX B The S1C6S2N7 I/O Memory MapK03K02K01K00––––HIGHHIGHHIGHHIGHLO

Strany 97 - S1C6SL27/S1C6S2B7

II-76 EPSON S1C6S2N7 TECHNICAL SOFTWAREAPPENDIX B THE S1C6S2N7 I/O MEMORY MAPR03R02R01BUZZERR00FOUT000000HIGHHIGHHIGHONHIGHONLOWLOWLOWOFFLOWOFFR03 OU

Strany 98 - S1C6S2B7 (CR oscillation)

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-77APPENDIX C TABLE OF THE ICE COMMANDSAPPENDIX C Table of the ICE Commands12345678910AssembleDisassembleDumpFill

Strany 99 - CD=built-in, Ta=25°C

II-78 EPSON S1C6S2N7 TECHNICAL SOFTWAREAPPENDIX C TABLE OF THE ICE COMMANDS11121314151617HistoryFileCoverageROM AccessTerminateICECommandDisplaySelfD

Strany 100 - 7.1 Plastic Package

S1C6S2N7 TECHNICAL SOFTWARE EPSON II-79APPENDIX D CROSS-ASSEMBLER PSEUDO-INSTRUCTION LISTAPPENDIX D Cross-assembler Pseudo-instruction ListItem No. P

Strany 101 - QFP6-60pin

S1C6S2N7 TECHNICAL HARDWARE EPSON I-7CHAPTER 2: POWER SUPPLY AND INITIAL RESETThe LCD system regulated voltage circuit use can be prohibited bysetting

Strany 102 - 8.1 Diagram of Pad Layout

AMERICAEPSON ELECTRONICS AMERICA, INC.- HEADQUARTERS -1960 E. Grand AvenueEI Segundo, CA 90245, U.S.A.Phone: +1-310-955-5300 Fax: +1-310-955-5400- S

Strany 103 - 8.2 Pad Coordinates

http://www.epson.co.jp/device/Technical ManualS1C6S2N7EPSON Electronic Devices WebsiteELECTRONIC DEVICES MARKETING DIVISIONFirst issue March, 1996Prin

Strany 104

NOTICENo part of this material may be reproduced or duplicated in any form or by any means without the written permission of SeikoEpson. Seiko Epson r

Strany 105 - Technical Software

I-8 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 2: POWER SUPPLY AND INITIAL RESETInitial ResetTo initialize the S1C6S2N7 Series circuits, an initial rese

Strany 106

S1C6S2N7 TECHNICAL HARDWARE EPSON I-9CHAPTER 2: POWER SUPPLY AND INITIAL RESETOscillation detectioncircuitThe oscillation detection circuit outputs th

Strany 107

I-10 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 2: POWER SUPPLY AND INITIAL RESETWhen, for instance, mask option D (K00*K01*K02*K03) isselected, an init

Strany 108

S1C6S2N7 TECHNICAL HARDWARE EPSON I-11CHAPTER 3: CPU, ROM, RAMCPU, ROM, RAMCPUThe S1C6S2N7 Series employs the S1C6200A core CPU, sothat register confi

Strany 109 - Software

I-12 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 3: CPU, ROM, RAM3.2 ROMThe built-in ROM, a mask ROM for the program, has acapacity of 1,536 × 12-bit ste

Strany 110

S1C6S2N7 TECHNICAL HARDWARE EPSON I-13CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)PERIPHERAL CIRCUITSAND OPERATIONPeripheral circuits (ti

Strany 111 - S1C6S2N7 Block Diagram

I-14 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)Table 4.1.1(a) I/O memory mapAddress CommentRegisterD3

Strany 112 - Program area

S1C6S2N7 TECHNICAL HARDWARE EPSON I-15CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)Table 4.1.1(b) I/O memory map* 1 Initial value followin

Strany 113 - Interrupt Vectors

I-16 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)Table 4.1.1(c) I/O memory mapAddress CommentRegisterD3

Strany 114 - Data Memory Map

S1C6S2N7 TECHNICAL HARDWARE EPSON I-17CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)Table 4.1.1(d) I/O memory map* 1 Initial value followin

Strany 115 - CHAPTER 1: CONFIGURATION

PREFACEThis manual is individualy described about the hardware and the softwareof the S1C6S2N7.I. S1C6S2N7 Technical HardwareThis part explains the fu

Strany 116

I-18 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)Table 4.1.1(e) I/O memory map* 1 Initial value followin

Strany 117

S1C6S2N7 TECHNICAL HARDWARE EPSON I-19CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)CR oscillation circuitThe S1C6S2N7 Series has

Strany 118

I-20 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)Input Ports (K00–K03)The S1C6S2N7 Series has a 4-bit g

Strany 119 - EPSON II-9

S1C6S2N7 TECHNICAL HARDWARE EPSON I-21CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)Fig. 4.3.3Input interrupt timingInput interrupt progra

Strany 120 - CHAPTER 2

I-22 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)Consequently, when the input terminal is in the active

Strany 121 - CHAPTER 2: INITIAL RESET

S1C6S2N7 TECHNICAL HARDWARE EPSON I-23CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)Table 4.3.1 list the input port control bits and their

Strany 122 - Initialize Program Example

I-24 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)Interrupt mask registers (0E8H)Masking the interrupt o

Strany 123 - Fig. 2.2.1

S1C6S2N7 TECHNICAL HARDWARE EPSON I-25CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)Output Ports (R00–R03)The S1C6S2N7 Series has a 4-bit

Strany 124 - Input Ports

I-26 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)The mask option enables the following output port sel

Strany 125 - Examples of input

S1C6S2N7 TECHNICAL HARDWARE EPSON I-27CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)FOUT (R00) When output port R00 is set for FOUT outpu

Strany 127 - Output Ports3.2

I-28 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)Output port data (0F3H)Sets the output data for the o

Strany 128 - Examples of output

S1C6S2N7 TECHNICAL HARDWARE EPSON I-29CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)Special output port data (0F3H D0)Controls the FOUT (

Strany 129 - EPSON II-19

I-30 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)Special output port data (0F3H D0, 0F3H D1)Controls t

Strany 130 - Special Use Output Ports3.3

S1C6S2N7 TECHNICAL HARDWARE EPSON I-31CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)I/O Ports (P00–P03)The S1C6S2N7 Series has a 4-bit gener

Strany 131 - Control of the spe

I-32 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)Input or output mode can be set for the four bits of I/O

Strany 132 - Examples of special

S1C6S2N7 TECHNICAL HARDWARE EPSON I-33CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)I/O port data (0F6H)I/O port data can be read and output

Strany 133 - EPSON II-23

I-34 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)I/O control register (0FCH D0)The input or output I/O po

Strany 134 - 3.4 I/O Ports

S1C6S2N7 TECHNICAL HARDWARE EPSON I-35CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)LCD Driver (COM0–COM3, SEG0–SEG25)The S1C6S2N7 Series h

Strany 135

I-36 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)Fig. 4.6.1Drive waveform for1/4 duty (1/3 bias)LCD ligh

Strany 136 - Examples of I/O port

S1C6S2N7 TECHNICAL HARDWARE EPSON I-37CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)Fig. 4.6.2Drive waveform for1/3 duty (1/3 bias)Frame fr

Strany 137 - EPSON II-27

The information of the product number changeConfiguration of product numberDevicesComparison table between new and previous numberS1C60 Family proc

Strany 138

I-38 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)Fig. 4.6.3Drive waveform for1/2 duty (1/3 bias)COM0COM1

Strany 139 - LCD Driver3.5

S1C6S2N7 TECHNICAL HARDWARE EPSON I-39CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)LCD lighting statusNot litLitSEG0–25SEG0–25Frame freque

Strany 140 - Control of the LCD

I-40 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)LCD lighting statusNot litLitSEG0–25Frame frequencySEG0

Strany 141 - (1/3 bias)

S1C6S2N7 TECHNICAL HARDWARE EPSON I-41CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)Switching betweendynamic and staticdriveThe S1C6S2N7 Se

Strany 142 - LCD driver control

I-42 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)(1) Segment allocationAs shown in Figure 4.l.1, the S1C

Strany 143 - D3 D2 D1 D0

S1C6S2N7 TECHNICAL HARDWARE EPSON I-43CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)(2) Drive dutyAccording to the mask option, either 1/4,

Strany 144 - 3.6 Timer

I-44 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)Table 4.6.2 shows the control bits of the LCD driver an

Strany 145 - Control of the timer

S1C6S2N7 TECHNICAL HARDWARE EPSON I-45CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)Clock TimerThe S1C6S2N7 Series has a built-in clock ti

Strany 146 - Examples of timer

I-46 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)The clock timer can interrupt on the falling edge of t

Strany 147 - EPSON II-37

S1C6S2N7 TECHNICAL HARDWARE EPSON I-47CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)Table 4.7.1 shows the clock timer control bits and the

Strany 149 - Control of the stop

I-48 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)Interrupt mask registers (0EBH D0–D2)These registers a

Strany 150 - Examples of stop

S1C6S2N7 TECHNICAL HARDWARE EPSON I-49CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)Stopwatch TimerThe S1C6S2N7 Series incorporates a

Strany 151 - A register

I-50 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)The stopwatch timer is configured as two four-bit

Strany 152 - SVD circuit and

S1C6S2N7 TECHNICAL HARDWARE EPSON I-51CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)The 10 Hz (approximate 10 Hz) and 1 Hz interrupts

Strany 153 - Example of SVD

I-52 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)Table 4.8.1 shows the stopwatch timer control bits

Strany 154 - Heavy load protec

S1C6S2N7 TECHNICAL HARDWARE EPSON I-53CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)1/100 sec stopwatch timer (0E2H)Data (BCD) of the

Strany 155 - EPSON II-45

I-54 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)SWRST Stopwatch timer reset (0F9H D0)This bit rese

Strany 156 - Examples of heavy

S1C6S2N7 TECHNICAL HARDWARE EPSON I-55CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)4.9Configuration of

Strany 157 - EPSON II-47

I-56 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)In the heavy load p

Strany 158 - Flowchart of operation

S1C6S2N7 TECHNICAL HARDWARE EPSON I-57CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)The following expla

Strany 159 - 3.9 Motor Driver

HardwareS1C6S2N7I. Technical Hardware

Strany 160 - Examples of motor

I-58 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)The S1C6S2N7 Series

Strany 161 - 3.10 Interrupt and Halt

S1C6S2N7 TECHNICAL HARDWARE EPSON I-59CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)Table 4.9.1 shows t

Strany 162

I-60 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)SVDONSVDDTSVD contr

Strany 163 - Control of interrupts

S1C6S2N7 TECHNICAL HARDWARE EPSON I-61CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)Stepping Motor DriverThe S1C6S2N7 Series has

Strany 164 - Input interrupt circuit

I-62 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)Drive pulseBy writing 1 to the FTRG register

Strany 165 - Timer interrupt circuit

S1C6S2N7 TECHNICAL HARDWARE EPSON I-63CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)Table 4.10.1 shows the motor driver control

Strany 166 - Stopwatch interrupt circuit

I-64 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)ISMD Interrupt factor flag (0ECH D0)This is

Strany 167 - Fig. 3.10.4

S1C6S2N7 TECHNICAL HARDWARE EPSON I-65CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)Interrupt and HALTThe S1C6S2N7 Series provides

Strany 168 - Active status

I-66 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)K00EIK00K01EIK01K02EIK02K03EIK03ISW0EISW0ISMDEI

Strany 169 - EPSON II-59

S1C6S2N7 TECHNICAL HARDWARE EPSON I-67CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)Table 4.11.1 shows the factors that generate in

Strany 171 - Interrupt vector map

I-68 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)The interrupt factor flags can be masked by the

Strany 172 - Internal interrupt circuit

S1C6S2N7 TECHNICAL HARDWARE EPSON I-69CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)When an interrupt request is input to the CPU,

Strany 173 - Examples of interrupt

I-70 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)Tables 4.11.4 (a) and (b) shows the interrupt c

Strany 174

S1C6S2N7 TECHNICAL HARDWARE EPSON I-71CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)Table 4.11.4 (b) Interrupt control bits (2)Addr

Strany 175 - EPSON II-65

I-72 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 5: BASIC EXTERNAL WIRING DIAGRAMBASIC EXTERNAL WIRING DIAGRAM(1) Piezo Buzzer Single Terminal DrivingCHA

Strany 176 - SUMMARY OF PROGRAMMING

S1C6S2N7 TECHNICAL HARDWARE EPSON I-73CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM(2) Piezo Buzzer Direct DrivingX'talCGC1–C5CpRCRCrystal oscillatorT

Strany 177

I-74 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSCHAPTER 6 ELECTRICAL CHARACTERISTICS6.1 Absolute Maximum RatingS1C6S2N7/S1C

Strany 178

S1C6S2N7 TECHNICAL HARDWARE EPSON I-75CHAPTER 6: ELECTRICAL CHARACTERISTICSRecommended Operating ConditionsS1C6S2N76.2S1C6S2A7ItemSupply voltageOscill

Strany 179 - EPSON II-69

I-76 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6SL27∗1 When the heavy load protection mode is set by software and the S

Strany 180

S1C6S2N7 TECHNICAL HARDWARE EPSON I-77CHAPTER 6: ELECTRICAL CHARACTERISTICS6.3 DC CharacteristicsS1C6S2N7/S1C6S2A7/S1C6S2B7Unless otherwise specifiedV

Strany 181 - EPSON II-71

HardwareS1C6S2N7 TECHNICAL HARDWARE EPSON I-iCONTENTSCONTENTSCHAPTER 1 INTRODUCTION... I-

Strany 182

I-78 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6SL27Unless otherwise specifiedVDD=0 V, VSS=-1.5 V, fosc=32.768 kHz, Ta=

Strany 183 - Registers specified

S1C6S2N7 TECHNICAL HARDWARE EPSON I-79CHAPTER 6: ELECTRICAL CHARACTERISTICS6.4 Analog Circuit Characteristics and Current ConsumptionS1C6S2N7 (Crystal

Strany 184

I-80 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2L7 (Crystal oscillation, Normal operating mode)Unless otherwise speci

Strany 185 - EPSON II-75

S1C6S2N7 TECHNICAL HARDWARE EPSON I-81CHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2B7 (Crystal oscillation, Normal operating mode)Unless otherwise speci

Strany 186

I-82 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2N7 (CR oscillation, Normal operating mode)Unless otherwise specifiedV

Strany 187 - EPSON II-77

S1C6S2N7 TECHNICAL HARDWARE EPSON I-83CHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2A7 (CR oscillation, Normal operating mode)Unless otherwise specifiedV

Strany 188

I-84 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2B7 (CR oscillation, Normal operating mode)Unless otherwise specifiedV

Strany 189 - EPSON II-79

S1C6S2N7 TECHNICAL HARDWARE EPSON I-85CHAPTER 6: ELECTRICAL CHARACTERISTICS6.5 Oscillation CharacteristicsOscillation characteristics will vary accord

Strany 190

I-86 EPSON S1C6S2N7 TECHNICAL HARDWARECHAPTER 6: ELECTRICAL CHARACTERISTICSS1C6S2N7 (CR oscillation)Unless otherwise specifiedVDD=0 V, VSS=-3.0 V, RCR

Strany 191 - Technical Manual

S1C6S2N7 TECHNICAL HARDWARE EPSON I-87CHAPTER 6: ELECTRICAL CHARACTERISTICS6.6 Motor Driver CharacteristicsUnless otherwise specifiedVDD=0 V, VSS=-1.5

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