Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Uživatelský manuál stáhnout pdf (Strana 18)

2 REGISTERS

EPSON

S1C33 FAMILY C33 PE CORE MANUAL

2.5 Trap Table Base Register (TTBR)

Symbol

TTBR

Size

32 bits

Initial value

0x00C00000*

Trap Table Base Register

R/W

The Trap Table Base Register (hereinafter referred to as the “TTBR”) is a 32-bit register that is used to store the

start address of the vector table to be referenced when an interrupt or exception occurs. During cold reset, the

TTBR is initialized to 0x00C00000*, and the program is executed from the address indicated by the reset vector.

TTBR is a read/writable register, and can be set to any address in the software. However, bits 9–0 in the TTBR are

fixed at 0 and cannot be accessed for writing. Therefore, the addresses that can be set in the TTBR are those that lie

on 1K-byte boundaries.

1K-byte boundary address 0000000000

091031

Fixed

(read only)

Figure 2.5.1 Trap Table Base Register (TTBR)

∗ The initial value (0xC00000 by default) can be changed by configuring the hardware parameters.

2.6 Arithmetic Operation Registers (ALR and AHR)

Symbol

ALR

AHR

Size

32 bits

Initial value

Indeterminate

Arithmetic Operation Low Register

Arithmetic Operation High Register

R/W

One of the special registers included in the C33 PE Core is the arithmetic operation register used in multiply

operations, which consists of the Arithmetic Operation Low Register (hereinafter referred to as the “ALR”) and the

Arithmetic Operation High Register (hereinafter referred to as the “AHR”). Each is a 32-bit data register that allows

data to be transferred to and from the general-purpose registers using load instructions. Multiply instructions use

the ALR and the AHR to store the 32 low-order bits and 32 high-order bits of the result of operation, respectively.

When initialized upon reset, the ALR and AHR become indeterminate.

2.7 Processor Identification Register (IDIR)

Symbol

IDIR

Size

32 bits

Initial value

0x06XXXXXX

Processor Identification Register

R/W

The Processor Identification Register (hereinafter referred to as the “IDIR”) is a 32-bit register that contains the

processor type, revision, and other information. The IDIR is a read-only register, and its readout value varies by

model.

The bit configuration in the IDIR is detailed below.

Processor type

01531 24

Revision

Undefined instruction code

0x06

Varies by model

0xXXXX

23 16

Indicates

C33 PE.

Varies depending on

the processor revision

and installed model.

Indicates the object code

when an undefined instruction

exception has occurred.

Readout value

Figure 2.7.1 Processor Identification Register (IDIR)

2.8 Debug Base Register (DBBR)

Symbol

DBBR

Size

32 bits

Initial value

0x00060000

Debug Base Register

R/W

The Debug Base Register (hereinafter referred to as the “DBBR”) is a 32-bit register that contains the base address

of a memory area used for debugging. The DBBR is a read-only register which, in the C33 PE Core, is fixed to

0x00060000.

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 180 181

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