Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Uživatelský manuál Strana 73

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7 DETAILS OF INSTRUCTIONS
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
65
and %rd, %rs
Function
Logical AND
Standard) rd
rd & rs
Extension 1) rd
rs & imm13
Extension 2) rd
rs & imm26
Code
15 12 11 8 7 4 3 0
0 0 1 1 0 0 1 0
r s r d
0x32__
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Flag
IE C V Z N
0
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Mode
Src: Register direct %rs = %r0 to %r15
Dst: Register direct
%rd = %r0 to %r15
CLK
One cycle
Description
(1) Standard
and
%rd,%rs ; rd rd & rs
The content of the rs register and that of the rd register are logically ANDed, and the result is
loaded into the rd register.
(2) Extension 1
ext
imm13
and
%rd,%rs ; rd rs & imm13
The content of the rs register and the zero-extended 13-bit immediate imm13 are logically
ANDed, and the result is loaded into the rd register. The content of the rs register is not altered.
(3) Extension 2
ext
imm13 ; = imm26(25:13)
ext
imm13 ; = imm26(12:0)
and
%rd,%rs ; rd rs & imm26
The content of the rs register and the zero-extended 26-bit immediate imm26 are logically
ANDed, and the result is loaded into the rd register. The content of the rs register is not altered.
(4) Delayed instruction
This instruction may be executed as a delayed instruction by writing it directly after a branch
instruction with the d bit. In this case, extension of the immediate by the ext instruction
cannot be performed.
Example
(1) and %r0,%r0 ; r0 = r0 & r0
(2)
ext 0x1
ext 0x1fff
and %r1,%r2 ; r1 = r2 & 0x00003fff
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