Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Uživatelský manuál Strana 43

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5 INSTRUCTION SET
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
35
5.11 Shift and Rotate Instructions
The instruction set of the C33 PE Core supports instructions to shift or rotate the register data.
srl Logical shift right
sll Logical shift left
sra Arithmetic shift right
sla Arithmetic shift left
rr Rotate right
rl Rotate left
The number of bits that can be shifted has been increased from the conventional 8 bits to 32 bits. Because 32-bit
shift is supported, new instructions have been added with extended functions. The number of bits to be shifted can
be specified in the range of 0 to 31 using the operand
imm5 or the rs register.
Example: srl %rd,imm5 Bits 031 logically shifted to the right
srl %rd,%rs Bits 031 logically shifted to the right
31
0 C
rd
srl Logical shift right
0
0
31C
rd
0
sll Logical shift left
31
0 C
MSB
Sign bit
rd
sra Arithmetic shift right
0
31C
rd
0
sla Arithmetic shift left
31
0 C
rd
rr Rotate right
31C
rd
0
rl Rotate left
The table below lists the number of bits shifted as specified by the rs register or the operand imm5.
Table 5.11.1 Number of Bits Shifted as Specified by imm5 or rs
imm5
rs
[5:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Number of bits
to be shifted
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
imm5
rs[5:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Number of bits
to be shifted
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bits 531 in the rs are not used.
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